{"id":8,"date":"2024-12-09T02:29:18","date_gmt":"2024-12-08T17:29:18","guid":{"rendered":"https:\/\/www.loicsylvestre.com\/?page_id=8"},"modified":"2025-09-02T17:24:17","modified_gmt":"2025-09-02T15:24:17","slug":"8-2","status":"publish","type":"page","link":"https:\/\/www.loicsylvestre.com\/","title":{"rendered":"Lo\u00efc Sylvestre"},"content":{"rendered":"\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-28f84493 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:25%\">\n<figure class=\"wp-block-image size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"847\" height=\"1024\" src=\"https:\/\/www.loicsylvestre.com\/wp-content\/uploads\/2025\/02\/ls-847x1024.jpg\" alt=\"\" class=\"wp-image-93\" style=\"width:173px;height:auto\" srcset=\"https:\/\/www.loicsylvestre.com\/wp-content\/uploads\/2025\/02\/ls-847x1024.jpg 847w, https:\/\/www.loicsylvestre.com\/wp-content\/uploads\/2025\/02\/ls-248x300.jpg 248w, https:\/\/www.loicsylvestre.com\/wp-content\/uploads\/2025\/02\/ls-768x929.jpg 768w, https:\/\/www.loicsylvestre.com\/wp-content\/uploads\/2025\/02\/ls.jpg 950w\" sizes=\"auto, (max-width: 847px) 100vw, 847px\" \/><\/figure>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:50%\">\n<p><br>IRIT<br>118 route de Narbonne<br>31062 Toulouse cedex 9<br>France<\/p>\n\n\n\n<p><em>mail: loic [DOT] sylvestre [AT] utoulouse [DOT] fr<\/em><\/p>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:25%\"><\/div>\n<\/div>\n\n\n<p>&nbsp;<\/p>\n<hr \/>\n<div id=\"content\">\n<p style=\"max-width: 40em;\">I am currently an associate professor at the <a href=\"https:\/\/www.univ-tlse3.fr\">University of Toulouse<\/a>, and member of the <a href=\"https:\/\/www.irit.fr\/departement\/architecture-systemes-reseaux\/equipe-traces\/\">TRACES<\/a> research team at IRIT. My research focuses on real-time embedded systems, hardware design and programming languages.<\/p>\n<p style=\"max-width: 40em;\">Previously, I was a post-doctoral researcher in the <a href=\"https:\/\/parkas.di.ens.fr\">PARKAS<\/a> team at INRIA Paris\/ENS. I hold a Ph.D in Computer Science from Sorbonne Universit\u00e9, conducted in the <a href=\"https:\/\/www-apr.lip6.fr\/web\/doku.php\">APR<\/a> team of the <a href=\"https:\/\/www.lip6.fr\/actualite\/personnes-fiche.php?ident=D2511\">LIP6<\/a> under the supervision of <a href=\"https:\/\/www-apr.lip6.fr\/~chaillou\/\">Emmanuel Chailloux<\/a> and <a href=\"https:\/\/dream.ispr-ip.fr\/members\/jocelyn-serot\/#page-content\">Jocelyn S\u00e9rot<\/a>. My thesis focused on the design and implementation of the <a href=\"https:\/\/github.com\/lsylvestre\/eclat\">Eclat<\/a> programming language, following a synchronous approach for mixing parallel computation (control-flow oriented) and interaction (data-flow oriented) on FPGAs.<\/p>\n<\/div>\n<h2 id=\"teaching\">Teaching (in French)<\/h2>\n<h4 id=\"teaching\">Universit\u00e9 de Toulouse<\/h4>\n<p>2025-2026<\/p>\n<ul>\n<li>Th\u00e9orie des langages (en Master 1)<\/li>\n<li>Bases de l&rsquo;architecture et des syst\u00e8mes (en Licence)<\/li>\n<li>Architecture des machines\u00a0(en Licence)<\/li>\n<\/ul>\n<h4 id=\"teaching\">Sorbonne Universit\u00e9<\/h4>\n<p>2024-2025<\/p>\n<ul>\n<li>responsable du cours de Compilation Avanc\u00e9e (en Master 1 STL)<\/li>\n<li>intervenant dans le cours de Paradigmes de Programmation Concurrente (en Master 2 STL)<\/li>\n<li><a href=\"https:\/\/www-licence.ufr-info-p6.jussieu.fr\/lmd\/licence\/2023\/ue\/LU2IN022-2024fev\/ACS\">Architectures Client-serveur<\/a> (4 TD, en Licence 2)<\/li>\n<\/ul>\n<p>2023-2024<\/p>\n<ul>\n<li><a href=\"https:\/\/moodle-sciences-23.sorbonne-universite.fr\/course\/info.php?id=4290\">Analyse de programmes et s\u00e9mantique<\/a> (TD, en Master 1)<\/li>\n<li><a href=\"https:\/\/www-apr.lip6.fr\/~chaillou\/Public\/enseignement\/2023-2024\/ca\/\">Compilation Avanc\u00e9e<\/a> (4 cours \/ 5 TD, en Master 1 STL)<\/li>\n<li><a href=\"https:\/\/www-licence.ufr-info-p6.jussieu.fr\/lmd\/licence\/2023\/ue\/LU2IN014-2024fev\/\">Architecture des ordinateurs<\/a> (TP, en Licence 2)<\/li>\n<\/ul>\n<p>2022-2023<\/p>\n<ul>\n<li>Analyse de programmes et s\u00e9mantique (TD, en Master 1 STL)<\/li>\n<li><a href=\"https:\/\/www-apr.lip6.fr\/~chaillou\/Public\/enseignement\/2022-2023\/pf\/\">Programmation fonctionnelle<\/a> (TP, en Licence 2)<\/li>\n<li><a href=\"https:\/\/www-licence.ufr-info-p6.jussieu.fr\/lmd\/licence\/2022\/ue\/LU2IN014-2023fev\/\">Architecture des ordinateurs<\/a> (TP, en Licence 2)<\/li>\n<\/ul>\n<p>2021-2022<\/p>\n<ul>\n<li>El\u00e9ments de programmation (TD et TP, en Licence 1)<\/li>\n<li><a href=\"https:\/\/www-apr.lip6.fr\/~chaillou\/Public\/enseignement\/2021-2022\/pf\/\">Programmation fonctionnelle<\/a> (TP, en Licence 2)<\/li>\n<li><a href=\"https:\/\/www-apr.lip6.fr\/~chaillou\/Public\/enseignement\/2021-2022\/ca\/\">Compilation Avanc\u00e9e<\/a> (TD, en Master 1 STL)<\/li>\n<li><a href=\"https:\/\/www-licence.ufr-info-p6.jussieu.fr\/lmd\/licence\/2021\/ue\/LU2IN014-2022fev\/\">Architecture des ordinateurs<\/a> (TP, en Licence 2)<\/li>\n<\/ul>\n<h2 id=\"software\">Software<\/h2>\n<ul>\n<li><a href=\"https:\/\/github.com\/lsylvestre\/eclat\">Eclat<\/a>, a compiler turning programs writen in Eclat (a functional-imperative, parallel, synchronous language) down to VHDL for reconfiguring FPGAs<\/li>\n<li><a href=\"https:\/\/github.com\/lsylvestre\/easy-check\">easy-check<\/a>, a library for easing writing exercices with automatic graders in <a href=\"https:\/\/github.com\/ocaml-sf\/learn-ocaml\">Learn-OCaml<\/a><\/li>\n<li><a href=\"https:\/\/github.com\/lsylvestre\/macle\">Macle <em>(ML Accelerator)<\/em><\/a>, a compiler for implementing hardware accelerators to be called by OCaml programs executed by <a href=\"https:\/\/github.com\/jserot\/O2B\">O2B<\/a> on FPGAs<\/li>\n<li><a href=\"https:\/\/github.com\/lsylvestre\/B2ML\">B2ML<\/a>, a compiler for generating OCaml code from <a href=\"https:\/\/en.wikipedia.org\/wiki\/B-Method\">B<\/a> specifications, part of the <a href=\"https:\/\/www.clearsy.com\/recherche-et-developpement\/lchip\/\">LCHIP<\/a> project.<\/li>\n<\/ul>\n<h2 id=\"publications\">Publications<\/h2>\n<ul>\n<li><strong>2025<\/strong> L. Sylvestre, J. S\u00e9rot, E. Chailloux : Programming parallelism on FPGAs with Eclat,\u00a0<em>International Journal of Parallel Programming (IJPP)<b> 53<\/b>, pp. 26-50, Springer Verlag (2025). DOI:<a href=\"https:\/\/doi.org\/10.1007\/s10766-025-00801-7\">10.1007\/s10766-025-00801-7<\/a> <\/em><em>(<a href=\"https:\/\/hal.science\/hal-05169350v1\"> HAL<\/a>)<\/em><\/li>\n<li><strong>2024<\/strong> L. Sylvestre, J. S\u00e9rot, E. Chailloux : Programming parallelism on FPGAs with Eclat, <em>17th International Symposium on High-Level Parallel Programming and Applications (HLPP &rsquo;24)<\/em> Pisa, Italy, pp. 69-88 &#8211; (<a href=\"https:\/\/hal.science\/hal-04772531v1\">HAL<\/a>)<\/li>\n<li><strong>2024<\/strong> L. Sylvestre, J. S\u00e9rot, E. Chailloux : Hardware implementation of OCaml using a synchronous functional language, <em>Practical Aspects of Declarative Languages (PADL &rsquo;24)<\/em>, Londres, United Kingdom (2024), pp. 151-168, Springer Nature Switzerland. DOI:<a href=\"https:\/\/link.springer.com\/chapter\/10.1007\/978-3-031-52038-9_10\">10.1007\/978-3-031-52038-9_10<\/a> &#8211; (<a href=\"https:\/\/hal.sorbonne-universite.fr\/hal-04401618v1\">HAL<\/a>)<\/li>\n<li><strong>2023<\/strong> L. Sylvestre, E. Chailloux, J. S\u00e9rot : Work-in-Progress: Mixing Computation and Interaction on FPGA, <em>International Conference on Embedded Software (EMSOFT &rsquo;23)<\/em> Hamburg, Germany, pp. 5-6, ACM. DOI:<a href=\"https:\/\/dl.acm.org\/doi\/10.1145\/3607890.3608467\">10.1145\/3607890.3608467<\/a> &#8211; (<a href=\"https:\/\/hal.sorbonne-universite.fr\/hal-04260840v1\"> HAL<\/a>)<\/li>\n<li><strong>2023<\/strong> L. Sylvestre, E. Chailloux, J. S\u00e9rot : Accelerating OCaml Programs on FPGA, <em>International Journal of Parallel Programming (IJPP), pp. 186-207, Springer Verlag (2023). DOI:<a href=\"https:\/\/link.springer.com\/article\/10.1007\/s10766-022-00748-z\">10.1007\/s10766-022-00748-z<\/a> &#8211; (<a href=\"https:\/\/hal.sorbonne-universite.fr\/hal-03991412v1\"> HAL<\/a>)<\/em><\/li>\n<li><strong>2022<\/strong> L. Sylvestre, E. Chailloux, J. S\u00e9rot : Accelerating OCaml Programs on FPGA, <em>15th International Symposium on High-Level Parallel Programming and Applications (HLPP 2022)<\/em> Porto, Portugal &#8211; (<a href=\"https:\/\/hal.sorbonne-universite.fr\/hal-03921136v1\"> HAL<\/a>)<\/li>\n<li><strong>2022<\/strong> L. Sylvestre, J. S\u00e9rot, E. Chailloux : \u201cA Virtual Machine Approach for High-level FPGA Programming\u201d,<br \/><em>IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM &rsquo;22)<\/em>, IEEE. <a href=\"https:\/\/ieeexplore.ieee.org\/document\/9786082\/\">10.1109\/FCCM53951.2022.9786082<\/a> &#8211; (<a href=\"https:\/\/hal.sorbonne-universite.fr\/hal-03921090v1\"> HAL<\/a>)<\/li>\n<li><strong>2022<\/strong> L. Sylvestre, J. S\u00e9rot, E. Chailloux : \u201cMacle : un langage d\u00e9di\u00e9 \u00e0 l\u2019acc\u00e9l\u00e9ration de programmes OCaml sur circuits FPGA\u201d, <em>Journ\u00e9es Francophones des Langages Applicatifs (JFLA &rsquo;22), pp. 93-109 &#8211; (<a href=\"https:\/\/hal.sorbonne-universite.fr\/hal-03626795v1\"> HAL<\/a>)<\/em><\/li>\n<li><strong>2020<\/strong> L. Sylvestre, E. Chailloux : \u201cExp\u00e9rimentations p\u00e9dagogiques en Learn-OCaml\u201d,<br \/><em>Journ\u00e9es Francophones des Langages Applicatifs (JFLA &rsquo;20) &#8211; (<a href=\"https:\/\/hal.sorbonne-universite.fr\/hal-03154266v1\"> HAL<\/a>)<\/em><\/li>\n<\/ul>\n<h2 id=\"talks\">Talks<\/h2>\n<ul>\n<li style=\"list-style-type: none;\">\n<ul>\n<li><a href=\"https:\/\/www.irif.fr\/seminaires\/programmation\/index\">groupe de travail Programmation<\/a>, IRIF\u00a0<em>(April 28, 2025)<\/em> \u2013 \u00ab Synth\u00e8se de circuits sur cibles FPGA : quel r\u00f4le pour les langages de programmation ? \u00bb<\/li>\n<li>Lab-STICC <em>(March 27, 2025)<\/em> \u2013 \u00ab Conception et synth\u00e8se d\u2019applications mat\u00e9rielles temporellement pr\u00e9dictibles : un retour d\u2019exp\u00e9rience \u00bb<\/li>\n<li>S\u00e9minaire TRACES, IRIT <em>(Marsh 20, 2025)<\/em> \u00a0\u2013 \u00ab Conception et synth\u00e8se d\u2019applications mat\u00e9rielles temporellement pr\u00e9dictibles : un retour d\u2019exp\u00e9rience \u00bb<\/li>\n<li>S\u00e9minaire Preuve de programmes, LMF <em>(March 12, 2025)<\/em> \u2013 \u00ab Conception d\u2019architectures mat\u00e9rielles fiables \u00e0 base de FPGA avec Eclat \u00bb<\/li>\n<li>S\u00e9minaire DISC, ISAE-SUPAERO <em>(March 7, 2025)<\/em> \u2013 \u00ab Conception de syst\u00e8mes r\u00e9actifs et programmation parall\u00e8le de haut niveau \u00e0 base d\u2019architectures FPGA \u00bb<\/li>\n<li>S\u00e9minaire Kairos, I3S\/INRIA <em>(March 3, 2025)<\/em> &#8211; Conception de syst\u00e8mes r\u00e9actifs et programmation parall\u00e8le de haut niveau \u00e0 base d\u2019architectures FPGA<\/li>\n<li><a href=\"https:\/\/www.univ-orleans.fr\/lifo\/seminaire.php?lang=fr#res590\">S\u00e9minaire du LIFO<\/a> <em>(January 25, 2025)<\/em> &#8211; Eclat : un langage synchrone pour la programmation s\u00fbre, expressive et efficace de circuits FPGA<\/li>\n<li><a href=\"https:\/\/discuss.ocaml.org\/t\/oups-december-2024\/15654\">Meetup OCaml (OUPS)<\/a> <em>(December 12, 2024)<\/em> &#8211; Safe, expressive and efficient FPGA programming<\/li>\n<li><a href=\"https:\/\/www-apr.lip6.fr\/web\/doku.php?id=apr:journees:ete2024\">Journ\u00e9es d&rsquo;\u00e9quipe APR \u00e0 Caen<\/a> <em>(May 31, 2024)<\/em> &#8211; Programmation FPGA de bas en haut et vice-versa<\/li>\n<li><a href=\"https:\/\/hackmd.io\/@kdesnos\/SJWHYpzPG\/https%3A%2F%2Fhackmd.io%2F%40kdesnos%2FB1s3UVFk0?type=book\">VAADER Serminar<\/a> <em>(May 24, 2024)<\/em> &#8211; En m\u00eame temps mais dans l\u2018ordre : une approche synchrone pour la programmation parall\u00e8le sur FPGA<\/li>\n<li><a href=\"https:\/\/parkas.di.ens.fr\/seminars.html\">S\u00e9minaire PARKAS <\/a> <em>(December 06, 2023)<\/em> &#8211; Une approche synchrone pour la<br \/>programmation haut-niveau de FPGA<\/li>\n<li><a href=\"https:\/\/rtsys.informatik.uni-kiel.de\/~biblio\/downloads\/Synchron23\/Day4\/Day4-1535-sylvestre-InteractionComputationFPGA.pdf\">SYNCHRON23<\/a> <em>(30 November, 2023)<\/em> &#8211; Mixing interaction and computation on FPGA<\/li>\n<li><a href=\"https:\/\/fct.ualg.pt\/seminarios-deei\">Semin\u00e1rios DEEI<\/a>, Universidade do Algarve <em>(3 November, 2023)<\/em> &#8211; Mixing interaction and computation on FPGA<\/li>\n<li><a href=\"https:\/\/wiki.f-si.org\/index.php?title=FSiC2023\">FSIC 2023<\/a> <em>(July 10, 2023)<\/em> &#8211; Mixing software abstractions for high-level FPGA programming<\/li>\n<li><a href=\"https:\/\/clap-hifi-lvp-2023.sciencesconf.org\/?lang=fr\">Journ\u00e9es CLAP-HiFi-LVP 2023, session du groupe de travail HiFi<\/a> (March 20, 2023) &#8211; M\u00e9lange de calcul et d&rsquo;interaction sur un FPGA<\/li>\n<li><a href=\"https:\/\/www-apr.lip6.fr\/APR\/journeeAPR2022f.pdf\"> Journ\u00e9e de l\u2019\u00e9quipe APR<\/a>, \u00c9cole des Mines, Paris (June 17, 2022) \u2013 \u00ab Acc\u00e9l\u00e9ration de programmes OCaml sur FPGA \u00bb\u00a0<\/li>\n<li><a href=\"https:\/\/gdr-gpl-2022.sciencesconf.org\/program\">Journ\u00e9es nationales du GDR GPL 2022, session du groupe de travail CLAP<\/a> <em>(June 7, 2022)<\/em> &#8211; Macle : un langage d\u00e9di\u00e9 \u00e0 l&rsquo;acc\u00e9l\u00e9ration de programmes OCaml sur FPGA<\/li>\n<li><a href=\"https:\/\/www-apr.lip6.fr\/~chaillou\/Public\/programmation\/2021-2022\/ls.html\">S\u00e9minaire IRILL<\/a> <em>(March 24, 2022) <\/em> &#8211; Macle : un langage d\u00e9di\u00e9 \u00e0 l&rsquo;acc\u00e9l\u00e9ration de programmes OCaml sur circuits FPGA<\/li>\n<li><a href=\"https:\/\/www-apr.lip6.fr\/web\/doku.php?id=apr:journees:ete2019\">Demi-journ\u00e9e de l&rsquo;\u00e9quipe APR<\/a> <em>(July 5, 2019)<\/em> &#8211; Portage de mat\u00e9riels p\u00e9dagogiques sur la plateforme Learn-OCaml (un assistant \u00e0 l&rsquo;enseignement du langage OCaml)<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<\/li>\n<\/ul>\n<div id=\"footer\" class=\"mb-5\"><hr \/><\/div>\n<p>&nbsp;<\/p>","protected":false},"excerpt":{"rendered":"<p>IRIT118 route de Narbonne31062 Toulouse cedex 9France mail: loic [DOT] sylvestre [AT] utoulouse [DOT] fr &nbsp; I am currently an<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-8","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.loicsylvestre.com\/index.php?rest_route=\/wp\/v2\/pages\/8","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.loicsylvestre.com\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.loicsylvestre.com\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.loicsylvestre.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.loicsylvestre.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=8"}],"version-history":[{"count":57,"href":"https:\/\/www.loicsylvestre.com\/index.php?rest_route=\/wp\/v2\/pages\/8\/revisions"}],"predecessor-version":[{"id":135,"href":"https:\/\/www.loicsylvestre.com\/index.php?rest_route=\/wp\/v2\/pages\/8\/revisions\/135"}],"wp:attachment":[{"href":"https:\/\/www.loicsylvestre.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=8"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}